Individual semiconductor devices in VLSI integrated circuits are interconnected by means of one or more patterned conductive layers overlying the semiconductor devices. It is particularly advantageous to provide a plurality of patterned conductive layers separated from one another and from the underlying semiconductor devices by layers of insulating material. This practice permits a higher density of interconnections per unit area than can be provided by a single patterned conductive layer, and simplifies design by permitting interconnection paths implemented in one conductive layer to cross over interconnection paths implemented in other conductive layers.
Multilevel interconnection structures are conventionally made by alternately depositing and patterning layers of conductive material, typically aluminum alloys such as Al-Si, and layers of insulating material, typically SiO.sub.2. The patterning of underlying layers defines a nonplanar topography which complicates reliable formation of overlying layers. In particular, the non-planar topography of underlying conductive layers is replicated in overlying insulating layers to provide vertical steps in the insulating layers. Moreover, small holes are formed in the insulating layers to permit interconnection to underlying conductive layers or device contacts.
The subsequent formation of conductive layers overlying the nonplanar topography of the insulating layers is complicated by thinning of the conductive layers at the tops of the steps, cusping or microcracking of the conductive layers at the bottoms of the steps, and formation of voids in the conductive layers in small via and contact holes, all of which can lead to high resistance interconnections or undesired open circuits. Moreover, uneven formation of the conductive layers reduces the resistance of the patterned conductive material to electromigration, reducing the reliability of the completed integrated circuit.
Patterning of the resulting conductive layers may also be complicated by the nonplanar topography. For example, conductive material at the bottom of steps is difficult to remove and may provide unwanted conductive paths between adjacent regions of a conductive layer.
The formation of further insulating layers is also complicated by the nonplanar topography of the conductive layers. Weaknesses are present in the insulating layers at the tops and bottoms of steps. Cracks form at such weaknesses, providing unwanted conductive paths between adjacent conductive layers. Narrow troughs between steps in the conductive layers are difficult to fill with commonly used insulating materials, such as SiO.sub.2 without the formation of voids.
The Resist Etch Back (REB) technique is frequently used to modify the nonplanar topography of insulating layers in an effort to minimize or avoid the above problems. In the REB technique, a thick layer of photoresist is formed on a nonplanar insulating layer and the photoresist is etched back until peaks or steps in the insulating layer topography are exposed, but valleys or troughs in the insulating layer topography are filled with remaining photoresist. The etching process is then controlled so that the etch rate of the insulating layer is substantially equal to the etch rate of the photoresist. Peaks or steps in the insulating layer topography are etched while valleys or troughs are protected by the photoresist so the height of the peaks or steps is reduced. After the etching is complete, remaining photoresist is removed and additional insulating material is deposited if required to build the insulating layer up to a desired thickness. The next conductive layer is then deposited on the insulating layer, which is now relatively smooth, and the conductive layer is patterned.
In related etch back planarization techniques, the photoresist may be replaced by other materials, such as Spin On Glass (SOG).
While etch back techniques reduce the height of peaks or steps in the insulating layer topography, they do not necessarily eliminate the sharp edges or vertical sidewalls of steps. These sharp edges and vertical sidewalls cause many of the problems referred to above, and such problems persist when conventional etch back techniques are used.
Etch back techniques are also subject to macroloading and microloading effects which can have a considerable impact on the results obtained in a production environment. The macroloading effect is a run to run or wafer to wafer variation of the relative etch rates of the insulating material and photoresist. Because the etch rates must be substantially equal to obtain an optimum reduction in step height, such variations cause a reduction in step height which is less than optimum. In severe cases, macroloading effects may actually accentuate deviations from a planar topography.
The microloading effect is enhanced localized etching of the photoresist in narrow valleys or troughs and at the edges of steps in the insulating layer. Microloading is primarily due to oxygen species liberated during etching of the insulating layer defining the side walls of the valleys, troughs or steps. The enhanced localized etching causes formation of sharp notches or trenches which in turn cause the problems referred to above.
The performance of etch back techniques can be improved somewhat by combining them with low pressure ion milling techniques, as described in co-pending U.S. application Ser. No. 199,489 filed May 27, 1988 in the name of Thomas Abraham. However, even this improved technique seeks to planarize a nonplanar topography instead of avoiding the formation of the nonplanar topography in the first place.
Some research facilities are studying the use of polyimide insulating layers in place of the more conventional SiO.sub.2 insulating layers. Unlike SiO.sub.2 insulating layers, polyamide insulating layers need not conform to the underlying topography and can therefore be deposited with substantially planar upper surfaces. Consequently most of the problems discussed above can be avoided without the use of etch back techniques by providing substantially planar insulating layers. Unfortunately, much more work is required to prove that polyimides can be used reliably in commercial device fabrication. As an insulator, SiO.sub.2 is still the preferred dielectric because of its proven compatibility with silicon devices and the accumulated experience with its use in commercial device fabrication.
Broadbent et al have recently proposed a Filled Interconnect Groove (FIG) technique for forming multilevel interconnect structures (IEEE Transactions on Electron Devices, Vol. 35, No. 7, pp. 952-956, July 1988). In the technique proposed by Broadbent et al, a substantially planar insulating layer of phosphosilicate glass is deposited by Chemical Vapour Depositon (CVD) over devices formed in a silicon substrate. The glass insulating layer is patterned to form grooves which extend through the glass insulating layer where interconnect metallization is desired. An adhesion bilayer consisting of 20 nm of tungsten and 20 nm of titanium is deposited by DC magnetron sputtering over the glass insulating layer and in the grooves. Tungsten is then deposited on the adhesion bilayer by CVD to form a tungsten blanket which covers the entire upper surface of the adhesion bilayer and fills the grooves. The tungsten blanket is then etched back to expose the glass insulating layer between the grooves, thereby providing a substantially planar interconnect structure.
Unfortunately, loading effects encountered during the etch back step reduce the effectiveness of the technique proposed by Broadbent et al. In particular, the local etch rate of the tungsten blanket is found to be dependent on the ratio between the surface area covered by tungsten and the surface area of exposed glass. Consequently tungsten is removed faster from portions of the structure where a relatively large surface area of glass is exposed than from portions of the structure where little or no glass is exposed. Thus, any nonuniformity in the deposition of the tungsten blanket which results in nonuniform thickness of the tungsten blanket can result in total removal of tungsten from grooves on one part of the structure before the glass between grooves is exposed on another part of the structure. This results in undesired open circuits and short circuits in the interconnect structure. Moreover, nonuniformity of the tungsten etch rate prevents matching of the tungsten etch rate to the glass etch rate across the entire surface of the structure as would be required for ideal planarity of the resulting structure.